This application claims the priority of Korean Patent Application No. 2004-79205, filed on Oct. 5, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a flat panel display (FPD) device, and more particularly, to a sync processor that determines signal safety on the basis of a horizontal/vertical synchronization signal generated in response to a data enable signal.
2. Description of the Related Art
FIG. 1 shows a data display area of a conventional LCD panel. Referring to FIG. 1, 1024 data lines and 768 gate lines are arranged, wherein the 1024 data lines are controlled by a horizontal synchronization signal (HSYNC) and the 768 gate lines are controlled by a vertical synchronization signal (VSYNC).
FIG. 2 shows waveforms appearing during a horizontal scanning period of an image signal. Referring to FIG. 2, a horizontal scanning period includes a pulse width period Thp, a back porch period Thb, a horizontal active period Thd, and a front porch period Thf of a horizontal sync signal HSYNC. The horizontal active period Thd is a period in which an actual image is displayed in row directions of a screen. The back porch period Thb and the front porch period Thf are periods in which optically blank areas are displayed at the left and right ends of a screen. During the horizontal active period Thd, 1024 data elements are sequentially supplied to the screen and a data enable signal DE is activated.
FIG. 3 shows waveforms appearing during a vertical scanning period of an image signal. Referring to FIG. 3, a vertical scanning period includes a pulse width period Tvp, a back porch period Tvb, a vertical active period Tvd, and a front porch period Tvf of a vertical sync signal VSYNC. The vertical active period Tvd is a period in which an image is actually displayed in column directions of a screen, and the back porch period Tvb and the front porch period Tvf are periods in which optically blank areas are displayed in the top and bottom ends of the screen. During the vertical active period Tvd, 768 elements data are sequentially supplied to the screen and a data enable signal DE is activated.
Meanwhile, since a LCD panel includes both a digital interface and an analog interface, the LCD panel needs to determine whether a received signal is an analog signal or a digital signal. A sync processor of a flat panel display (FPD) determines a mode and safety of an input signal on the basis of a horizontal sync signal HSYNC and a vertical sync signal VSYNC, where the horizontal sync signal HSYNC and the vertical sync signal VSYNC are analog signals or digital signals. The sync processor provides an interrupt signal to a micro-controller unit (MCU) whenever a source, a frequency, or a polarity of an input signal is changed, thereby indicating that the input signal is unstable. The MCU changes a LCD panel 400 from a mute state to a normal display state if no interrupt signal is generated within a predetermined time period.
The sync processor determines a mode and safety of an input signal using a horizontal sync signal HSYNC and a vertical sync signal VSYNC output from a receiving terminal Rx of a DVI (Digital Video Interface) or using a data enable signal DE. However, when the horizontal sync signal HSYNC and the vertical sync signal VSYNC are used, if an input signal, which is defined in a separate sync mode based on a DVI standard, is not output in the separate sync mode from a graphic card, it is impossible to determine the mode of the input signal. Also, since the horizontal sync signal HSYNC and the vertical sync signal VSYNC are commonly transmitted through a B channel of R/G/B data channels to a transmitting terminal Tx of the DVI, when a DVI clock signal and the B channel are stable and the R/G channels are unstable, the MCU determines that DVI inputs are stable so that, in this case, abnormal images are still displayed.
Also, when signal safety is determined on the basis of the data enable signal DE, an analog sync processing circuit must be separately constructed.
To solve these problems, the fact that a data enable signal DE of a DVI is transmitted through three R/G/B channels is advantageously used. That is, since a horizontal sync signal HSYNC and a vertical sync signal VSYNC generated according to the data enable signal DE become unstable when at least one of the three R/G/B channels is unstable, it is possible to easily determine signal safety.